C-DAC has successfully completed the design, development and validation of a series of 32-bit /64-bit Single and Multi-core superscalar out-of-order high performance processors based on the open source RISC-V Instruction Set Architecture with multilevel Caches, Memory Management Unit and Coherent Interconnect. C-DAC has also integrated a wide range of silicon proven system and peripheral IPs and has successfully ported the SoCs on FPGA boards, booted Linux/ FreeRTOS, run various applications and verified the performance with standard benchmarks. The complete software ecosystem comprising of the Board Support Packages, SDK with integrated tool chain, IDE plug-ins and Debugger for development, testing and debugging is also available.


VEGA ET1031 is a small and efficient 3-stage in-order 32-bit RISC-V processor core. This Microprocessor can be used as an effective workhorse in low power IoT applications.

Key features :

  • RISC-V (RV32IM) Instruction Set Architecture
    • 32-bit RISC-V with 32 integer registers (I extension)

    • Integer multiplication and division (M extension)

  • 3-stage in-order pipeline implementation

  • Harvard architecture (separate instruction and data buses)

  • Machine privilege mode

Applications :

  • Sensor fusion

  • Smart Meter

  • System supervisors

  • Remote sensors

  • Small IoT devices

  • Wearable devices

  • Toy and electronic education equipment

  • 8/16-bit applications

  • Industrial networking